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» Designing a DHT for Low Latency and High Throughput
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MTV
2007
IEEE
121views Hardware» more  MTV 2007»
15 years 3 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
ICMI
2004
Springer
162views Biometrics» more  ICMI 2004»
15 years 3 months ago
When do we interact multimodally?: cognitive load and multimodal communication patterns
Mobile usage patterns often entail high and fluctuating levels of difficulty as well as dual tasking. One major theme explored in this research is whether a flexible multimodal in...
Sharon L. Oviatt, Rachel Coulston, Rebecca Lunsfor...
CASES
2006
ACM
15 years 1 months ago
High-performance packet classification algorithm for many-core and multithreaded network processor
Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based cla...
Duo Liu, Bei Hua, Xianghui Hu, Xinan Tang
IPCCC
2006
IEEE
15 years 3 months ago
A novel queue management mechanism for improving performance of multihop flows in IEEE 802.11s based mesh networks
– Wireless Mesh networks exploit multi-hop wireless communications between Access Points to replace wired infrastructure. However, in multi-hop networks, effective bandwidth decr...
Nagesh Nandiraju, Deepti S. Nandiraju, Dave Cavalc...
CIT
2006
Springer
15 years 1 months ago
A Contention Window Based Differentiation Mechanism for providing QoS in Wireless LANs
Running real time applications over wireless LANs is becoming common place. These applications require QoS. But the most widely used wireless LAN, IEEE 802.11, does not have QoS s...
Mayank Mishra, Anirudha Sahoo