377 search results - page 7 / 76 » Designing a DHT for Low Latency and High Throughput |
ICMCS
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper describes the Stanford P2P Multicast (SPPM) streaming system that employs an overlay architecture specifically designed for low delay video applications. In order to p...
EUROPAR
2001
Springer
15 years 2 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
FAST
2010
14 years 12 months ago
2010
A content-addressable storage (CAS) system is a valuable tool for building storage solutions, providing efficiency by automatically detecting and eliminating duplicate blocks; it ...
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
WCW
2004
Springer
15 years 2 months ago
2004
Springer
Internet overlay services must adapt to the substrate network topology and link properties to achieve high performance. A common overlay structure management layer is desirable fo...