377 search results - page 9 / 76 » Designing a DHT for Low Latency and High Throughput |
HIPEAC
2010
Springer
15 years 6 months ago
2010
Springer
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpos...
ICASSP
2011
IEEE
14 years 1 months ago
2011
IEEE
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
SBACPAD
2007
IEEE
15 years 3 months ago
2007
IEEE
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...