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115
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DAC
2006
ACM
15 years 9 months ago
Hierarchical power distribution and power management scheme for a single chip mobile processor
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, E...
117
Voted
CISIS
2008
IEEE
15 years 10 months ago
On the Potential of NoC Virtualization for Multicore Chips
As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifte...
Jose Flich, Samuel Rodrigo, José Duato, Tho...
DAC
1998
ACM
16 years 4 months ago
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
Yehia Massoud, Steve S. Majors, Tareq Bustami, Jac...
DAC
2001
ACM
16 years 4 months ago
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
Li Chen, Xiaoliang Bai, Sujit Dey
HPCA
2007
IEEE
16 years 4 months ago
Implications of Device Timing Variability on Full Chip Timing
As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This pap...
Murali Annavaram, Ed Grochowski, Paul Reed