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ASPLOS
2006
ACM
15 years 10 months ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...
SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
15 years 9 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
15 years 3 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
AMEC
2004
Springer
15 years 9 months ago
Designing Auctions for Deliberative Agents
Abstract. In many settings, bidding agents for auctions do not know their preferences a priori. Instead, they must actively determine them through deliberation (e.g., information p...
Kate Larson, Tuomas Sandholm
HPCA
2008
IEEE
16 years 4 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...