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JSA
2008
94views more  JSA 2008»
15 years 3 months ago
Energy reduction through crosstalk avoidance coding in networks on chip
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cri...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
15 years 1 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
ATAL
2011
Springer
14 years 3 months ago
Incentive design for adaptive agents
We consider a setting in which a principal seeks to induce an adaptive agent to select a target action by providing incentives on one or more actions. The agent maintains a belief...
Yiling Chen, Jerry Kung, David C. Parkes, Ariel D....
GLVLSI
1998
IEEE
124views VLSI» more  GLVLSI 1998»
15 years 8 months ago
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. ...
TC
2008
15 years 3 months ago
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
On-chip networks (OCNs) have been proposed to solve the increasing scale and complexity of the designs in nanoscale multicore VLSI designs. The concept of irregular meshes is an im...
Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Ken...