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DATE
2005
IEEE
117views Hardware» more  DATE 2005»
15 years 9 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
IEEEPACT
2000
IEEE
15 years 8 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
ARVLSI
1999
IEEE
162views VLSI» more  ARVLSI 1999»
15 years 8 months ago
Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip
The ability of animals to select a limited region of sensory space for scrutiny is an important factor in dealing with cluttered or complex sensory environments. Such an attention...
Timothy K. Horiuchi, Ernst Niebur
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 7 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
FAC
2008
97views more  FAC 2008»
15 years 4 months ago
A functional formalization of on chip communications
This paper presents a formal model and a systematic approach to the validation of communication tures at a high level of abstraction. This model is described mathematically by a fu...
Julien Schmaltz, Dominique Borrione