Sciweavers

4394 search results - page 118 / 879
» Designing agent chips
Sort
View
TC
2008
15 years 3 months ago
Secure Memory Accesses on Networks-on-Chip
Security is gaining relevance in the development of embedded devices. Toward a secure system at each level of design, this paper addresses security aspects related to Network-on-Ch...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...
ARC
2010
Springer
126views Hardware» more  ARC 2010»
15 years 2 months ago
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challe...
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyse...
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
15 years 1 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
CAL
2010
15 years 1 months ago
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
HPCA
2011
IEEE
14 years 7 months ago
Shared last-level TLBs for chip multiprocessors
Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as c...
Abhishek Bhattacharjee, Daniel Lustig, Margaret Ma...