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NOCS
2008
IEEE
15 years 10 months ago
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
Abstract— In this paper, we discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach i...
Zheng Shi, Alan Burns
NOCS
2008
IEEE
15 years 10 months ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...
NOCS
2008
IEEE
15 years 10 months ago
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang,...
VTS
2007
IEEE
103views Hardware» more  VTS 2007»
15 years 10 months ago
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
ISCAS
2007
IEEE
158views Hardware» more  ISCAS 2007»
15 years 10 months ago
Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects
Abstract— This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj–driver) suitable for driving of global interconnects with large c...
José C. García, Juan A. Montiel-Nels...