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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 4 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
DAC
2000
ACM
16 years 23 days ago
The role of custom design in ASIC Chips
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
William J. Dally, Andrew Chang
ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
15 years 5 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler
DAC
2010
ACM
15 years 1 months ago
Network on chip design and optimization using specialized influence models
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
Cristinel Ababei
CCECE
2006
IEEE
15 years 5 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya