Sciweavers

4394 search results - page 140 / 879
» Designing agent chips
Sort
View
ASPDAC
2000
ACM
99views Hardware» more  ASPDAC 2000»
15 years 8 months ago
Reuse and protection of intellectual property in the SpecC system
— In system-level design, the key to cope with the complexities involved with System-on-Chip (SOC) designs, is the reuse of Intellectual Property (IP). With the increasing demand...
Rainer Dömer, Daniel Gajski
DAC
2008
ACM
16 years 5 months ago
Robust chip-level clock tree synthesis for SOC designs
A key problem that arises in System-on-a-Chip (SOC) designs of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS is done by merging all the clock trees belonging to differ...
Anand Rajaram, David Z. Pan
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
15 years 11 months ago
Gate sizing for large cell-based designs
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
Stephan Held
CEEMAS
2003
Springer
15 years 9 months ago
Airports for Agents: An Open MAS Infrastructure for Mobile Agents
Airports for Agents1 (AA) is an implemented distributed multi-agent infrastructure designed for dynamic and unstable Internet environment. The infrastructure consists of platforms ...
Jan Tozicka
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
15 years 10 months ago
Double-via-driven standard cell library design
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Run...