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ISCAS
2006
IEEE
79views Hardware» more  ISCAS 2006»
15 years 10 months ago
A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application
—In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT ...
Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van
99
Voted
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
15 years 10 months ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
VLSI
2005
Springer
15 years 9 months ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
TCAD
2010
118views more  TCAD 2010»
14 years 10 months ago
Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore
Abstract--Microfluidics-based biochips enable the precise control of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and they integrat...
Krishnendu Chakrabarty, Richard B. Fair, Jun Zeng
VLSID
2004
IEEE
168views VLSI» more  VLSID 2004»
16 years 4 months ago
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design
Watermarking is the process that embeds data called a watermark into a multimedia object for its copyright protection. The digital watermarks can be visible to a viewer on careful...
Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Nam...