4394 search results - page 144 / 879 » Designing agent chips |
107
Voted
ISLPED
2006
ACM
15 years 10 months ago
2006
ACM
In this paper, we identify the key challenges that oppose subthreshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges. Categorie...
139
click to vote
ICES
2003
Springer
15 years 9 months ago
2003
Springer
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
121
click to vote
ISPD
1998
ACM
15 years 8 months ago
1998
ACM
In this paper, we present a performance-driven softmacro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also pr...
130
click to vote
ICCAD
2001
IEEE
16 years 1 months ago
2001
IEEE
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
104
click to vote
DELTA
2006
IEEE
15 years 10 months ago
2006
IEEE
— Design, Verification and Test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnost...