4394 search results - page 146 / 879 » Designing agent chips |
132
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ITC
2003
IEEE
15 years 9 months ago
2003
IEEE
An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus pr...
143
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DSD
2007
IEEE
15 years 4 months ago
2007
IEEE
The universal underlying assumption made today is that Systems on chip must maintain 100% correctness regardless of the application. This work advocates the concept that some appl...
117
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MEMOCODE
2007
IEEE
15 years 10 months ago
2007
IEEE
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
112
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
158
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RTAS
2006
IEEE
15 years 10 months ago
2006
IEEE
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...