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INTEGRATION
2008
183views more  INTEGRATION 2008»
14 years 11 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
SASO
2009
IEEE
15 years 6 months ago
Generic Self-Adaptation to Reduce Design Effort for System-on-Chip
We investigate a generic self-adaptation method to reduce the design effort for System-on-Chip (SoC). Previous self-adaptation solutions at chip-level use circuitries which have b...
Andreas Bernauer, Oliver Bringmann, Wolfgang Rosen...
HIPEAC
2011
Springer
13 years 11 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
NOCS
2007
IEEE
15 years 6 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
ATS
2003
IEEE
110views Hardware» more  ATS 2003»
15 years 5 months ago
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...
Yu-Chiun Lin, Shi-Yu Huang