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ISSS
2002
IEEE
126views Hardware» more  ISSS 2002»
15 years 9 months ago
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with th...
Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali...
CODES
1996
IEEE
15 years 8 months ago
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
The TaSCA environment for hardware/software co-design of control dominated systems implemented on a single chip includes a novel approach to the system exploration phase for the e...
Alessandro Balboni, William Fornaciari, Donatella ...
ANCS
2007
ACM
15 years 8 months ago
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
DELTA
2004
IEEE
15 years 8 months ago
Towards Analog and Mixed-Signal SOC Design with SystemC-AMS
Systems-on-Chip (SoCs) are heterogeneous by nature as they may integrate digital, analog, RF hardware as well as software components or non electrical parts such as sensors or act...
Alain Vachoux, Christoph Grimm, Karsten Einwich
FTEDA
2007
78views more  FTEDA 2007»
15 years 4 months ago
Design Automation of Real-Life Asynchronous Devices and Systems
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks i...
Alexander Taubin, Jordi Cortadella, Luciano Lavagn...