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FPL
2006
Springer
137views Hardware» more  FPL 2006»
15 years 8 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
CASES
2001
ACM
15 years 8 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
115
Voted
ASPDAC
2005
ACM
119views Hardware» more  ASPDAC 2005»
15 years 6 months ago
CMP aware shuttle mask floorplanning
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
EVOW
2010
Springer
15 years 11 months ago
Evolving Individual Behavior in a Multi-agent Traffic Simulator
Abstract. In this paper, we illustrate the use of evolutionary agents in a multiagent system designed to describe the behavior of car drivers. Each agent has the selfish objective ...
Ernesto Sánchez, Giovanni Squillero, Albert...
131
Voted
TVLSI
1998
135views more  TVLSI 1998»
15 years 4 months ago
Wave-pipelining: a tutorial and research survey
— Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of hig...
Wayne P. Burleson, Maciej J. Ciesielski, Fabian Kl...