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ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
15 years 5 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
ACSD
2004
IEEE
124views Hardware» more  ACSD 2004»
15 years 3 months ago
A Behavioral Type Inference System for Compositional System-on-Chip Design
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc s...
Jean-Pierre Talpin, David Berner, Sandeep K. Shukl...
DAC
2007
ACM
16 years 24 days ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
15 years 6 months ago
Variability-aware robust design space exploration of chip multiprocessor architectures
Abstract— In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufactu...
Gianluca Palermo, Cristina Silvano, Vittorio Zacca...