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ISQED
2010
IEEE
194views Hardware» more  ISQED 2010»
16 years 25 days ago
Accelerating trace computation in post-silicon debug
— Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2...
Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aam...
DATE
2009
IEEE
101views Hardware» more  DATE 2009»
16 years 21 days ago
Flow regulation for on-chip communication
Abstract—We propose (σ, ρ)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communicat...
Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alista...
DATE
2009
IEEE
103views Hardware» more  DATE 2009»
16 years 21 days ago
A set-based mapping strategy for flash-memory reliability enhancement
—With wide applicability of flash memory in various application domains, reliability has become a very critical issue. This research is motivated by the needs to resolve the lif...
Yuan-Sheng Chu, Jen-Wei Hsieh, Yuan-Hao Chang, Tei...
VTC
2007
IEEE
109views Communications» more  VTC 2007»
16 years 6 days ago
A Reliability-Aware LDPC Code Decoding Algorithm
— With the continuing downscaling of microelectronic technology, chip reliability becomes a great threat to the design of future complex microelectronic systems. Hence increasing...
Matthias Alles, Torben Brack, Norbert Wehn
ISCAS
2006
IEEE
79views Hardware» more  ISCAS 2006»
15 years 12 months ago
Chip-scale magnetic sensing and control of nanoparticles and nanorods
— We report on a system designed for the magnetic control of nanoparticles and nanorods. This is accomplished by arrays of current-carrying wires (electromagnets) and the associa...
Edward Choi, Zhiyong Gu, D. Gracias, Andreas G. An...