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ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
16 years 2 months ago
Optimizing the Thermal Behavior of Subarrayed Data Caches
Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density...
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
16 years 2 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
ISCAS
2008
IEEE
95views Hardware» more  ISCAS 2008»
16 years 11 days ago
Wireless neural signal acquisition with single low-power integrated circuit
—We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-µm 2P3M BiCMOS process, ...
Reid R. Harrison, Ryan J. Kier, Bradley Greger, Fl...
VTS
2008
IEEE
83views Hardware» more  VTS 2008»
16 years 10 days ago
LS-TDF: Low-Switching Transition Delay Fault Pattern Generation
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
Jeremy Lee, Mohammad Tehranipoor
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
16 years 9 days ago
Thermally robust clocking schemes for 3D integrated circuits
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Ta...