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ISQED
2011
IEEE
398views Hardware» more  ISQED 2011»
14 years 10 months ago
Switching constraint-driven thermal and reliability analysis of Nanometer designs
As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors...
Srini Krishnamoorthy, Vishak Venkatraman, Yuri Apa...
HPCA
2006
IEEE
16 years 6 months ago
CMP design space exploration subject to physical constraints
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
Yingmin Li, Benjamin C. Lee, David Brooks, Zhigang...
ICCAD
2005
IEEE
108views Hardware» more  ICCAD 2005»
16 years 3 months ago
A routing algorithm for flip-chip design
— The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this paper,...
Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Ch...
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
16 years 1 months ago
Exploiting narrow-width values for thermal-aware register file designs
—Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras, Sung Woo ...
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
16 years 19 days ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...