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106
Voted
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 9 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
15 years 10 months ago
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor
Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Ta...
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
15 years 9 months ago
High-throughput decoder for low-density parity-check code
— We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regula...
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Iken...
110
Voted
CEC
2009
IEEE
15 years 7 months ago
JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator
This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous...
Olivier Brousse, Jérémie Guillot, Th...
110
Voted
AI
2007
Springer
15 years 7 months ago
Pattern Classification in No-Limit Poker: A Head-Start Evolutionary Approach
We have constructed a poker classification system which makes informed betting decisions based upon three defining features extracted while playing poker: hand value, risk, and agg...
Brien Beattie, Garrett Nicolai, David Gerhard, Rob...