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DAC
2007
ACM
16 years 25 days ago
Multi-Core Design Automation Challenges
The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the k...
John A. Darringer
VLSID
2002
IEEE
106views VLSI» more  VLSID 2002»
16 years 6 days ago
SWASAD: An ASIC Design for High Speed DNA Sequence Matching
This paper presents the Smith and Waterman Algorithm-Specific ASIC Design (SWASAD) project. This is a hardware solution that implements the S&W algorithm.. The SWASAD is an imp...
Tony Han, Sri Parameswaran
DATE
2008
IEEE
120views Hardware» more  DATE 2008»
15 years 6 months ago
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder
Chip reliability becomes a great threat to the design of future microelectronic systems with the continuation of the progressive downscaling of CMOS technologies. Hence increasing...
Matthias May, Matthias Alles, Norbert Wehn
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
15 years 5 months ago
Design space exploration for minimizing multi-project wafer production cost
- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle floopla...
Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-...
ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
15 years 4 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...