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ASPDAC
1995
ACM
77views Hardware» more  ASPDAC 1995»
15 years 3 months ago
A scheduling algorithm for synthesis of bus-partitioned architectures
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi T...
BMCBI
2007
104views more  BMCBI 2007»
14 years 12 months ago
A comparison of Affymetrix gene expression arrays
Background: Affymetrix GeneChips™ are an important tool in many facets of biological research. Recently, notable design changes to the chips have been made. In this study, we us...
Mark D. Robinson, Terence P. Speed
ISQED
2005
IEEE
116views Hardware» more  ISQED 2005»
15 years 5 months ago
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...
Subhrajit Bhattacharya, John A. Darringer, Daniel ...
ATAL
2000
Springer
15 years 4 months ago
Performance of Coordinating Concurrent Hierarchical Planning Agents Using Summary Information
Abstract. Recent research has provided methods for coordinating the individually formed concurrent hierarchical plans (CHiPs) of a group of agents in a shared environment. A reason...
Bradley J. Clement, Edmund H. Durfee
DATE
1999
IEEE
92views Hardware» more  DATE 1999»
15 years 4 months ago
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
Peter Feldmann, Sharad Kapur, David E. Long