4394 search results - page 55 / 879 » Designing agent chips |
JNCA
2007
14 years 11 months ago
2007
As the line rates standards are changing frequently to provide higher bit rates, the routers design has become very challenging due to the need for new wire-speed router’s netwo...
ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
114
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JSA
2010
14 years 6 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
105
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HPCA
2000
IEEE
15 years 4 months ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
SAC
2003
ACM
15 years 5 months ago
2003
ACM
Recently, researchers have created many platforms and applications for mobile agents; however, current Agent-Oriented Software Engineering (AOSE) methodologies have yet not fully ...