4394 search results - page 61 / 879 » Designing agent chips |
PDP
2010
IEEE
15 years 6 months ago
2010
IEEE
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to upd...
DAC
2009
ACM
16 years 26 days ago
2009
ACM
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilizat...
VLSID
2007
IEEE
16 years 7 days ago
2007
IEEE
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...