4394 search results - page 69 / 879 » Designing agent chips |
ETS
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
ARC
2007
Springer
15 years 6 months ago
2007
Springer
Abstract. In this paper, we present a systematic design and implementation of reconfigurable interconnects on demand. The proposed on-chip interconnection network provides identic...
FPL
2007
Springer
15 years 6 months ago
2007
Springer
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
127
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DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
126
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DATE
2010
IEEE
15 years 5 months ago
2010
IEEE
—This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to...