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ICCD
2008
IEEE
120views Hardware» more  ICCD 2008»
16 years 3 months ago
Near-optimal oblivious routing on three-dimensional mesh networks
— The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip architecture innovations. One direction is in the extens...
Rohit Sunkam Ramanujam, Bill Lin
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
16 years 3 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
ICS
2009
Tsinghua U.
16 years 28 days ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
16 years 27 days ago
Hardware-accelerated gradient noise for graphics
A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking te...
Josef B. Spjut, Andrew E. Kensler, Erik Brunvand
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
16 years 16 days ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...