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CASES
2005
ACM
15 years 7 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
CDC
2008
IEEE
125views Control Systems» more  CDC 2008»
15 years 5 months ago
Efficient waypoint tracking hybrid controllers for double integrators using classical time optimal control
This paper is a response to requests from several respected colleagues in academia for a careful writeup of the classical time-optimal control based hybrid controllers that we have...
Haitham A. Hindi, Lara S. Crawford, Rong Zhou, Cra...
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
15 years 5 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
DT
2000
88views more  DT 2000»
15 years 5 months ago
Postsilicon Validation Methodology for Microprocessors
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
Hemant G. Rotithor
TVLSI
2002
144views more  TVLSI 2002»
15 years 4 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail