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ITC
1995
IEEE
124views Hardware» more  ITC 1995»
15 years 3 months ago
An Experimental Chip to Evaluate Test Techniques: Experiment Results
This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and tes...
Siyad C. Ma, Piero Franco, Edward J. McCluskey
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
15 years 1 months ago
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...
Sushu Zhang, Karam S. Chatha
CSREAESA
2006
15 years 1 months ago
Chip OS: new architecture for next generation embedded system
Nowadays embedded system, hardware/software technology has progressed prosperously. In many field of industrial manufacture and people life, embedded system is indispensable. Rece...
Tianzhou Chen, Yi Lian, Wei Hu
PPL
2008
117views more  PPL 2008»
14 years 12 months ago
Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips
This discussion paper explores the problems of operating systems support when implementing concurrency controls at the level of the instruction set in processors designed for mult...
Chris R. Jesshope
ICCD
2007
IEEE
139views Hardware» more  ICCD 2007»
15 years 8 months ago
Statistical simulation of chip multiprocessors running multi-program workloads
This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to ...
Davy Genbrugge, Lieven Eeckhout