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131
Voted
DATE
2009
IEEE
178views Hardware» more  DATE 2009»
15 years 10 months ago
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constr...
Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Sam...
ISPASS
2007
IEEE
15 years 10 months ago
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhan...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 8 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
118
Voted
AAMAS
2002
Springer
15 years 3 months ago
The Implications of Philosophical Foundations for Knowledge Representation and Learning in Agents
Abstract. The purpose of this research is to show the relevance of philosophical theories to agent knowledge base (AKB) design, implementation, and behaviour. We will describe how ...
Nicholas Lacey, Mark Lee
CASES
2006
ACM
15 years 9 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh