17 search results - page 3 / 4 » Designing an FPGA SoC Using a Standardized IP Block Interfac... |
162
Voted
FPL
2006
Springer
15 years 5 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
101
Voted
CODES
2006
IEEE
15 years 7 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
126
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DAC
1999
ACM
15 years 6 months ago
1999
ACM
ion model or flexible PCB solutions cannot offer a valid solution for the next millinium SoCs . James G. Dougherty, Integrated Systems Silicon LTD, Belfast, Northern Ireland ISS an...
102
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ICCD
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
140
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DT
2006
15 years 1 months ago
2006
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...