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CAD
2011
Springer
14 years 6 months ago
Industrial design using interpolatory discrete developable surfaces
Design using free-form developable surfaces plays an important role in manufacturing industry. Currently most commercial systems can only support converting free-form surfaces int...
Yong-Jin Liu, Kai Tang, Wen-Yong Gong, Tie-Ru Wu
FMCAD
2007
Springer
15 years 6 months ago
Improved Design Debugging Using Maximum Satisfiability
In today's SoC design cycles, debugging is one of the most time consuming manual tasks. CAD solutions strive to reduce the inefficiency of debugging by identifying error sourc...
Sean Safarpour, Hratch Mangassarian, Andreas G. Ve...
VTC
2010
IEEE
242views Communications» more  VTC 2010»
15 years 1 months ago
A Cross-Layer Design Based on Geographic Information for Cooperative Wireless Networks
—Most of geographic routing approaches in wireless ad hoc and sensor networks do not take into consideration the medium access control (MAC) and physical layers when designing a ...
Teck Aguilar, Mohamed Chedly Ghedira, Syue-Ju Syue...
NN
2007
Springer
267views Neural Networks» more  NN 2007»
15 years 2 months ago
Modeling of gene regulatory networks with hybrid differential evolution and particle swarm optimization
In the last decade, recurrent neural networks (RNNs) have attracted more efforts in inferring genetic regulatory networks (GRNs), using time series gene expression data from micro...
Rui Xu, Ganesh K. Venayagamoorthy, Donald C. Wunsc...
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
13 years 10 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang