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GECCO
2008
Springer
261views Optimization» more  GECCO 2008»
15 years 6 months ago
SSNNS -: a suite of tools to explore spiking neural networks
We are interested in engineering smart machines that enable backtracking of emergent behaviors. Our SSNNS simulator consists of hand-picked tools to explore spiking neural network...
Heike Sichtig, J. David Schaffer, Craig B. Laramee
NCA
2010
IEEE
15 years 3 months ago
Genetic algorithm-based training for semi-supervised SVM
The Support Vector Machine (SVM) is an interesting classifier with excellent power of generalization. In this paper, we consider applying the SVM to semi-supervised learning. We p...
Mathias M. Adankon, Mohamed Cheriet
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
16 years 5 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
103
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SMI
2008
IEEE
101views Image Analysis» more  SMI 2008»
15 years 11 months ago
Fairing wireframes in industrial surface design
Wireframe is a modeling tool widely used in industrial geometric design. The term wireframe refers to two sets of curves, with the property that each curve from one set intersects...
Yu-Kun Lai, Yong-Jin Liu, Yu Zang, Shi-Min Hu
ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
15 years 11 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...