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» Designing and Building Parallel Program
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ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
15 years 8 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
114
Voted
IPPS
2002
IEEE
15 years 7 months ago
Implementing the NAS Benchmark MG in SAC
SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. How...
Clemens Grelck
125
Voted
IEEEPACT
2000
IEEE
15 years 6 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
203
Voted
WAE
2001
281views Algorithms» more  WAE 2001»
15 years 3 months ago
Using PRAM Algorithms on a Uniform-Memory-Access Shared-Memory Architecture
The ability to provide uniform shared-memory access to a significant number of processors in a single SMP node brings us much closer to the ideal PRAM parallel computer. In this pa...
David A. Bader, Ajith K. Illendula, Bernard M. E. ...
CLUSTER
2006
IEEE
15 years 2 months ago
A taxonomy of application scheduling tools for high performance cluster computing
Application scheduling plays an important role in high-performance cluster computing. Application scheduling can be classified as job scheduling and task scheduling. This paper pre...
Jiannong Cao, Alvin T. S. Chan, Yudong Sun, Sajal ...