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DATE
2006
IEEE
195views Hardware» more  DATE 2006»
15 years 5 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
DATE
2000
IEEE
94views Hardware» more  DATE 2000»
15 years 3 months ago
Shared Memory Implementations of Synchronous Dataflow Specifications
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...
Praveen K. Murthy, Shuvra S. Bhattacharyya
VLSISP
2008
123views more  VLSISP 2008»
14 years 11 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
PPOPP
2010
ACM
15 years 8 months ago
The LOFAR correlator: implementation and performance analysis
LOFAR is the first of a new generation of radio telescopes. Rather than using expensive dishes, it forms a distributed sensor network that combines the signals from many thousands...
John W. Romein, P. Chris Broekema, Jan David Mol, ...
GPCE
2005
Springer
15 years 4 months ago
Implicitly Heterogeneous Multi-stage Programming
Previous work on semantics-based multi-stage programming (MSP) language design focused on homogeneous designs, where the generating and the generated languages are the same. Homoge...
Jason Eckhardt, Roumen Kaiabachev, Emir Pasalic, K...