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107
Voted
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
15 years 10 months ago
Limiting the number of dirty cache lines
Abstract—Caches often employ write-back instead of writethrough, since write-back avoids unnecessary transfers for multiple writes to the same block. For several reasons, however...
Pepijn J. de Langen, Ben H. H. Juurlink
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
15 years 10 months ago
A highly resilient routing algorithm for fault-tolerant NoCs
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will so...
David Fick, Andrew DeOrio, Gregory K. Chen, Valeri...
99
Voted
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
15 years 10 months ago
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
—Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced i...
Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuy...
SP
2009
IEEE
144views Security Privacy» more  SP 2009»
15 years 10 months ago
Native Client: A Sandbox for Portable, Untrusted x86 Native Code
This paper describes the design, implementation and evaluation of Native Client, a sandbox for untrusted x86 native code. Native Client aims to give browser-based applications the...
Bennet Yee, David Sehr, Gregory Dardyk, J. Bradley...
102
Voted
IMC
2009
ACM
15 years 10 months ago
Understanding slow BGP routing table transfers
Researchers and network operators often say that BGP table transfers are slow. Despite this common knowledge, the reasons for slow BGP transfers are not well understood. This pape...
Zied Ben-Houidi, Mickael Meulle, Renata Teixeira