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DSN
2007
IEEE
15 years 6 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
90
Voted
ISCAS
2007
IEEE
94views Hardware» more  ISCAS 2007»
15 years 6 months ago
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
95
Voted
IPSN
2007
Springer
15 years 5 months ago
Harbor: software-based memory protection for sensor nodes
Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no...
Ram Kumar, Eddie Kohler, Mani B. Srivastava
HPCS
2006
IEEE
15 years 5 months ago
Toward a Software Infrastructure for the Cyclops-64 Cellular Architecture
This paper presents the initial design of the Cyclops-64 (C64) system software infrastructure and tools under development as a joint effort between IBM T.J. Watson Research Center...
Juan del Cuvillo, Weirong Zhu, Ziang Hu, Guang R. ...
78
Voted
ASPLOS
2006
ACM
15 years 5 months ago
Improving software security via runtime instruction-level taint checking
Current taint checking architectures monitor tainted data usage mainly with control transfer instructions. An alarm is raised once the program counter becomes tainted. However, su...
Jingfei Kong, Cliff Changchun Zou, Huiyang Zhou