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SRDS
2007
IEEE
15 years 10 months ago
The Fail-Heterogeneous Architectural Model
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
Marco Serafini, Neeraj Suri
116
Voted
OOPSLA
2007
Springer
15 years 10 months ago
Synthesizing reactive systems from LSC requirements using the play-engine
Live Sequence Charts (LSCs) is a scenario-based language for modeling object-based reactive systems with liveness properties. A tool called the Play-Engine allows users to create ...
Hillel Kugler, Cory Plock, Amir Pnueli
ICCAD
1998
IEEE
76views Hardware» more  ICCAD 1998»
15 years 8 months ago
Functional debugging of systems-on-chip
Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip...
Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra
ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
14 years 8 months ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti
SIGMOD
2003
ACM
140views Database» more  SIGMOD 2003»
16 years 4 months ago
The Design of an Acquisitional Query Processor For Sensor Networks
We discuss the design of an acquisitional query processor for data collection in sensor networks. Acquisitional issues are those that pertain to where, when, and how often data is...
Samuel Madden, Michael J. Franklin, Joseph M. Hell...