114 search results - page 15 / 23 » Designing for Xilinx XC6200 FPGAs |
ASAP
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
113
click to vote
ISSS
1998
IEEE
15 years 5 months ago
1998
IEEE
In this paper, we propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP proce...
123
click to vote
CHES
2009
Springer
16 years 1 months ago
2009
Springer
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
122
click to vote
RECONFIG
2008
IEEE
15 years 7 months ago
2008
IEEE
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
171
click to vote
ERSA
2009
14 years 11 months ago
2009
Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the...