114 search results - page 6 / 23 » Designing for Xilinx XC6200 FPGAs |
FCCM
2002
IEEE
15 years 2 months ago
2002
IEEE
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...
FPGA
2003
ACM
15 years 2 months ago
2003
ACM
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer line...
113
click to vote
FPGA
2001
ACM
15 years 2 months ago
2001
ACM
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
FPL
2004
Springer
15 years 3 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
FCCM
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...