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IPPS
2005
IEEE
15 years 6 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 6 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
ITCC
2005
IEEE
15 years 6 months ago
Zonal Rumor Routing for Wireless Sensor Networks
has to be relayed to nodes interested in those events. Moreover, nodes may also generate queries to find events they are interested in. Thus there is a need to route the informatio...
Tarun Banka, Gagan Tandon, Anura P. Jayasumana
IWIA
2005
IEEE
15 years 6 months ago
Malware Defense Using Network Security Authentication
Malware defenses have primarily relied upon intrusion fingerprints to detect suspicious network behavior. While effective for discovering computers that are already compromised,...
Joseph V. Antrosio, Errin W. Fulp
MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
15 years 6 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
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