1959 search results - page 348 / 392 » Designing for spatial competence |
102
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DAC
2005
ACM
16 years 1 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
105
Voted
VTC
2008
IEEE
15 years 7 months ago
2008
IEEE
— Transmit preprocessing employed at the basestation (BS) has been proposed for simplifying the design of the mobile receiver. Provided that the channel impulse response (CIR) of...
121
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ICS
2007
Tsinghua U.
15 years 6 months ago
2007
Tsinghua U.
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a singl...
101
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CODES
2005
IEEE
15 years 6 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
113
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GLVLSI
2005
IEEE
15 years 6 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...