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» Designing hardware with dynamic memory abstraction
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DATE
2010
IEEE
110views Hardware» more  DATE 2010»
15 years 2 months ago
An RDL-configurable 3D memory tier to replace on-chip SRAM
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
Marco Facchini, Paul Marchal, Francky Catthoor, Wi...
ASPDAC
2004
ACM
102views Hardware» more  ASPDAC 2004»
15 years 1 months ago
A dynamic element matching circuit for multi-bit delta-sigma modulators
Abstract-A 30k-gate dynamic element matching circuit for bandpass modulators with a 4-bit quantizer is designed by using 0.35-
Ryozo Katoh, Shin-ya Kobayashi, Takao Waho
105
Voted
ARC
2006
Springer
85views Hardware» more  ARC 2006»
15 years 1 months ago
Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking
Abstract. This paper presents a hardware architecture for UNIX password cracking using Hellman's time-memory trade-off; it is the first hardware design for a key search machin...
Nele Mentens, Lejla Batina, Bart Preneel, Ingrid V...
DAC
2004
ACM
15 years 10 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
162
Voted
CC
2009
Springer
132views System Software» more  CC 2009»
15 years 10 months ago
Implementation and Use of Transactional Memory with Dynamic Separation
Abstract. We introduce the design and implementation of dynamic separation (DS) as a programming discipline for using transactional memory. Our approach is based on the programmer ...
Andrew Birrell, Johnson Hsieh, Martín Abadi...