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» Designing hardware with dynamic memory abstraction
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ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
15 years 3 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
DATE
2009
IEEE
136views Hardware» more  DATE 2009»
15 years 4 months ago
A file-system-aware FTL design for flash-memory storage systems
Abstract—As flash memory became popular over various platforms, there is a strong demand on the performance degradation problem, due to the special characteristics of flash mem...
Po-Liang Wu, Yuan-Hao Chang, Tei-Wei Kuo
APCCAS
2006
IEEE
224views Hardware» more  APCCAS 2006»
14 years 11 months ago
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment
Abstract-- Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory pl...
Masanori Hariyama, Michitaka Kameyama
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
15 years 6 months ago
Formal model of data reuse analysis for hierarchical memory organizations
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
Ilie I. Luican, Hongwei Zhu, Florin Balasa
SIPEW
2009
Springer
127views Hardware» more  SIPEW 2009»
15 years 2 months ago
Investigating Cache Parameters of x86 Family Processors
Abstract. The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance ...
Vlastimil Babka, Petr Tuma