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» Designing hardware with dynamic memory abstraction
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ASPLOS
2010
ACM
15 years 4 months ago
Dynamic filtering: multi-purpose architecture support for language runtime systems
This paper introduces a new abstraction to accelerate the readbarriers and write-barriers used by language runtime systems. We exploit the fact that, dynamically, many barrier exe...
Tim Harris, Sasa Tomic, Adrián Cristal, Osm...
IROS
2009
IEEE
198views Robotics» more  IROS 2009»
15 years 4 months ago
Scalable learning for object detection with GPU hardware
Abstract— We consider the problem of robotic object detection of such objects as mugs, cups, and staplers in indoor environments. While object detection has made significant pro...
Adam Coates, Paul Baumstarck, Quoc V. Le, Andrew Y...
PLDI
1994
ACM
15 years 1 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
WEA
2005
Springer
120views Algorithms» more  WEA 2005»
15 years 3 months ago
Distilling Router Data Analysis for Faster and Simpler Dynamic IP Lookup Algorithms
Abstract. We consider the problem of fast IP address lookup in the forwarding engines of Internet routers. We analyze over 2400 public snapshots of routing tables collected over ...
Filippo Geraci, Roberto Grossi
85
Voted
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 2 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...