453 search results - page 28 / 91 » Designing hardware with dynamic memory abstraction |
ISCA
2010
IEEE
14 years 11 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Coherent read misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. We propose Tempor...
WADS
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. Algorithms dealing with massive data sets are usually designed for I/O-efficiency, often captured by the I/O model by Aggarwal and Vitter. Another aspect of dealing with ...
93
Voted
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
: Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics ...
WMPI
2004
ACM
15 years 3 months ago
2004
ACM
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...