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» Designing hardware with dynamic memory abstraction
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HASE
1997
IEEE
15 years 1 months ago
A Mechanism for Communicating in Dynamically Reconfigurable Embedded Systems
Abstract: We present a time-bounded state-based communication mechanism for dynamically reconfigurable embedded systems. The mechanism is a single-processor, low-overhead version o...
Mehrdad Hassani, David B. Stewart
ASPDAC
1995
ACM
110views Hardware» more  ASPDAC 1995»
15 years 1 months ago
Current and charge estimation in CMOS circuits
: CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the tot...
Sanjay Dhar, Dave J. Gurney
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
15 years 4 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
15 years 2 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
SIGCOMM
2000
ACM
15 years 1 months ago
Memory-efficient state lookups with fast updates
Routers must do a best matching pre x lookup for every packet solutions for Gigabit speeds are well known. As Internet link speeds higher, we seek a scalable solution whose speed ...
Sandeep Sikka, George Varghese