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» Designing hardware with dynamic memory abstraction
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ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Low-power techniques for network security processors
Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and ...
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiu...
ICCD
2006
IEEE
124views Hardware» more  ICCD 2006»
15 years 6 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili
ICPADS
2006
IEEE
15 years 3 months ago
Memory and Network Bandwidth Aware Scheduling of Multiprogrammed Workloads on Clusters of SMPs
Symmetric Multiprocessors (SMPs), combined with modern interconnection technologies are commonly used to build cost-effective compute clusters. However, contention among processor...
Evangelos Koukis, Nectarios Koziris
CA
1999
IEEE
15 years 2 months ago
Fast Synthetic Vision, Memory, and Learning Models for Virtual Humans
This paper presents a simple and efficient method of modeling synthetic vision, memory, and learning for autonomous animated characters in real-time virtual environments. The mode...
James J. Kuffner Jr., Jean-Claude Latombe
CODES
2007
IEEE
15 years 4 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer