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» Designing hardware with dynamic memory abstraction
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ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 2 months ago
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...
André Seznec, Stephen Felix, Venkata Krishn...
DATE
2008
IEEE
113views Hardware» more  DATE 2008»
15 years 4 months ago
Compositional, dynamic cache management for embedded chip multiprocessors
This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. The repa...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
15 years 4 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
SENSYS
2006
ACM
15 years 3 months ago
Capsule: an energy-optimized object storage system for memory-constrained sensor devices
Recent gains in energy-efficiency of new-generation NAND flash storage have strengthened the case for in-network storage by data-centric sensor network applications. This paper ...
Gaurav Mathur, Peter Desnoyers, Deepak Ganesan, Pr...
DAC
2002
ACM
15 years 10 months ago
Scheduler-based DRAM energy management
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...